1. Field of the Invention
The present invention relates to a semiconductor structure. More particularly, the present invention relates to a semiconductor structure that causes higher stress in the channel direction of a MOS transistor, and to a method for fabricating the same.
2. Description of the Related Art
In advanced metal-oxide-semiconductor (MOS) process, a stress layer is usually formed over a MOS transistor to improve the electron or hole mobility in the channel. In a MOS process of 65 nm or below, a compressive stress layer is formed over a PMOS transistor to cause compressive stress in its channel direction and improve hole mobility, while a tensile stress layer is formed over an NMOS transistor to cause tensile stress in its channel direction and improve electron mobility. Thereby, the driving currents are increased improving the performance of the product.
FIG. 1 illustrates a cross-sectional view of a semiconductor structure including a MOS transistor and a stress layer in the prior art. The structure includes a substrate 10, a MOS transistor 12 and a stress layer 24 over the same. The transistor 12 includes a gate structure 14 including gate dielectric 18 on the substrate 10 and a gate 16 thereon, a spacer 20 on the sidewall of the gate structure 14, a source/drain (S/D) extension region 21 in the substrate 10 beside the gate structure 14, and an S/D region 22 in the substrate 10 beside the spacer 20. When the transistor 12 is a PMOS (or NMOS) transistor, the stress layer 24 is a compressive (or tensile) stress layer that applies a compressive (or tensile) stress in the direction of the channel 26.
However, with the development of electronic industry, a higher performance is always required for semiconductor devices. It is promising to find a way to further raise the stress in the channel direction and improve the hole or electron mobility.